1. Field of the Invention
The present invention relates to semiconductor memory devices, more particularly, to DRAM (dynamic random access memory) type semiconductor memory devices that allow improved data holding characteristics. The present invention also relates to semiconductor memory devices that are most suitable for combining especially with logic circuits.
2. Description of the Related Art
FIG. 14 is a circuit diagram showing a configuration of a memory cell of a conventional DRAM (dynamic random access memory). In FIG. 14, numeral 100 denotes a memory cell, WL denotes a word line, BL denotes a bit line, 101 denotes an access transistor, 102 denotes a capacitor, and VCP denotes a cell plate power supply. The memory cell 100 includes one access transistor 101 and one capacitor 102. The drain of the access transistor 101 is connected to one end of the capacitor 102, the gate of the access transistor 101 is connected to the word line WL, the source of the access transistor 101 is connected to the bit line BL, and the other end of the capacitor 102 is connected to the cell plate power supply VCP.
Conventionally, in order to improve holding characteristics of logic data that is stored in the capacitor 102 of the memory cell 100, a configuration has been proposed in which, if the access transistor 101 is made of an n-channel transistor, when the access transistor is off, that is, the word line WL is at low level, a voltage is applied that is lower than a low voltage of a bit line when the bit line BL is activated. Also, a configuration has been proposed in which, if the access transistor 101 is made of a p-channel transistor, when the access transistor 101 is off, that is, the word line WL is at high level, a voltage is applied that is higher than a high voltage of a bit line when the bit line BL is activated (Japanese Laid-Open Patent Publication No. 8-63964).
As a circuit configuration for generating the voltage, a voltage boost circuit according to the charge pumping method generally is proposed (U.S. Pat. No. 6,147,914). Charge pumping allows a voltage higher than an external power source or a voltage lower than a ground potential to be generated, and there is no need for applying those voltages from the outside. Charge pumping is a method for generating a high voltage by periodically switching one node of a capacitor between high level and low level, and supplying the high voltage via a transistor.
In voltage generating circuits according to conventional charge pumping, the current capability can be improved by enlarging the capacitor circuit or by shortening the switching cycle of the capacitor. However, if the capacitor is enlarged, the circuit area is also enlarged, and this causes problems with regard to cost. Further, if the switching cycle is shortened, the circuit area also is enlarged because a drive circuit having a higher capability is required, thereby increasing current consumption.
Therefore, with the foregoing in mind, it is an object of the present invention to provide a semiconductor memory device whose circuit area is comparatively small and that improves the holding characteristics for data in the memory cell.
In order to achieve the above object, the semiconductor memory according to the present invention includes: a plurality of dynamic random access memory cells each having an access transistor (p-channel transistor) whose drain is connected to a bit line, whose gate is connected to one of a plurality of word lines, and whose source is connected to a capacitive element; a plurality of word line drive circuits that are connected to the plurality of word lines; and a word line voltage generator that is connected to the plurality of word line drive circuits. A first power source (Vdd) that is supplied externally is supplied to a sense amplifier for driving the bit line. The word line voltage generator receives the first power source and a second power source (Vdd3) that is supplied externally, generates a voltage that is by a predetermined voltage closer to a voltage of the second power source than the voltage of the first power source, and supplies the generated voltage to the plurality of word line drive circuits as a word line drive voltage (Vwl).
According to this characteristic configuration, an optimum off voltage of the word line that allows minimizing of a leakage current can be supplied as a voltage that is supplied to the plurality of dynamic random access memory cells, and a semiconductor memory device having a comparatively small circuit area without the requirement for a charge pump circuit or the like can be achieved by stepping-down the voltage of the second power source.
In the semiconductor memory device according to the present invention, it is preferable that the word line voltage generator includes: a first comparator (a first operational amplifier circuit) for comparing the word line drive voltage (Vwl) that is supplied to the word line drive circuit with a first reference voltage (Vref), and controlling conduction between a signal line of the word line drive voltage and the second power source (Vdd3); a first reference voltage generating circuit (Vdd reference load) for generating a voltage proportional to the voltage of the first power source (Vdd) as a second reference voltage (Vdl); a second reference voltage generating circuit (offset load) for generating a third reference voltage (Vpoi) from a second node that is connected through a transistor that is diode-connected to a first node to which the first reference voltage is applied; and a second comparator (a second operational amplifier circuit) for determining the first reference voltage by comparing the second reference voltage (Vdl) and the third reference voltage (Vpoi).
In this case, the voltage of the first power source has positive polarity, and the voltage of the second power source (for example, 3.3V) is higher than the voltage of the first power source (for example, 1.5 V), and the word line drive voltage (Vwl) is approximately 0.4 V higher than the voltage of the first power source (Vdd), or it is higher, by a voltage generated through a diode connection of a p-channel transistor having an identical configuration to the access transistor, than a voltage proportional to the voltage of the first power source.
In addition, it is preferable that the first reference voltage generating circuit (Vdd reference load) generates a second reference voltage (Vdl) by resistively dividing a voltage between the first power source (Vdd) and ground, and the second reference voltage generating circuit (offset load) includes: a first resistive element that is connected in series with a transistor that is diode-connected between the first node and the second node; and a second resistive element that is connected between the second node and the ground, and generates the third reference voltage (Vpoi) based on a voltage that is generated across the second resistive element.
With the word line voltage generator having a configuration mentioned above, the voltage Vdd3 of the second power source, which is higher than the voltage Vdd of the first power source that is supplied to the memory cells, is supplied to first and second comparators. The first and the second reference voltage generators and the second comparator (collectively referred to as xe2x80x9creference voltage generating circuitxe2x80x9d) generate a voltage that is higher, by a voltage generated through a diode connection of the p-channel transistor, than a voltage proportional to the voltage Vdd of the external power source as the first reference voltage (Vref), and the first comparator outputs a voltage that is equal to the first reference voltage Vref as a word line drive voltage Vwl, so that in a wide range of external voltages Vdd, a channel leakage current when the memory cell is off can be reduced most efficiently. Thus, there is no need for generating a voltage boost power source by providing a charge pump circuit, and a semiconductor memory device having a comparatively small circuit area can be achieved.
In addition, it is preferable that the semiconductor memory device is formed with a logic circuit and an analog circuit on a single semiconductor chip, the semiconductor chip includes a plurality of input/output portions (I/O) that are used for connection with the outside, and a power source that is supplied to the plurality of I/Os and the analog circuit is shared with the second power source.
According to this configuration, the number of the power sources that are supplied to the semiconductor chip can be reduced.
Further, in the semiconductor memory device according to the present invention, it is preferable that the film thickness of a gate oxide film of transistors that constitute the first and the second comparators to which a high voltage (Vdd3) is supplied is larger than that of a gate oxide film of the access transistor to which a lower voltage (Vdd) is supplied, so that reliability of the gate oxide film of the transistors that constitute the first and the second comparators can be ensured.
Further, in the semiconductor device according to the present invention, it is preferable that the film thickness of the gate oxide film of the transistors that constitute the first and the second comparators to which a high voltage (Vdd3) is supplied is larger than that of the gate oxide film of the access transistor to which a lower voltage (Vdd) is supplied, and the gate oxide film of the transistors that constitute the first and the second comparators is manufactured in the same manufacturing step as a gate oxide film of transistors that constitute the plurality of I/Os and the analog circuit to which a high voltage (Vdd3) is supplied. Thus, the reliability of the gate oxide film of the transistors that constitute the first and the second comparators, the plurality of I/Os, and the analog circuit can be ensured, and manufacturing cost can be kept down.
Further, in the semiconductor memory device according to the present invention, it is preferable that a gate oxide film of transistors that constitute the plurality of word line drive circuits to which a high voltage (Vdd3) is supplied is manufactured in the same manufacturing step as the gate oxide film of the transistors that constitute the first and the second comparators to which a high voltage (Vdd3) is also supplied. Thus, the reliability of the gate oxide film of the transistors that constitute the plurality of word line drive circuits can be ensured.
Further, in the semiconductor memory device according to the present invention, it is preferable that the gate oxide film of the transistors that constitute the plurality of word line drive circuits to which a high voltage (Vwl) is supplied is manufactured in the same manufacturing step as the gate oxide film of the transistors that constitute the first and the second comparators to which a high voltage (Vdd3) is also supplied and the gate oxide film of the transistors that constitute the plurality of I/Os and the analog circuit. Thus, the reliability of the gate oxide film of the transistors that constitute the plurality of word line drive circuits can be ensured, and manufacturing cost can be kept down.
Further, in the semiconductor memory device according to the present invention, it is preferable that a capacitive element of the plurality of dynamic random access memory cells is made of second p-channel transistors, and that the semiconductor memory device according to the present invention is manufactured by a general logic process, so that the semiconductor memory device according to the present invention can be achieved without increasing manufacturing cost.
Further, in the semiconductor memory device according to the present invention, it is preferable that the word line voltage generator generates a voltage obtained by adding a first offset voltage to the voltage of the first power source when a control signal (burn-in signal NBI) that is input is at a first voltage level (high level) (during normal operation), and generates a voltage obtained by adding a second offset voltage that is lower than the first offset voltage to a voltage of the first power source when the control signal is at a second voltage level (low level) (when a burn-in test is conducted).
This configuration allows lowering of a first reference voltage Vref, that is, an off voltage of the word line WL when the burn-in test is conducted, and allows unnecessarily high voltage from being applied to the word line WL to be prevented, even if a high voltage is applied as an external power source Vdd.